module test;

  reg reset;
  reg clk;
  wire [3:0] value;
  initial
     begin
	// The following two system commands create a file for gtkview
	// You may want to delete them if using verilogger-pro
      $dumpfile("icounter.vcd");
      $dumpvars ;
	// Authomatically monitor variables "reset" or "value" 
      $monitor("Time = %g reset = %b count = %b",$time, reset, value);
      reset = 0;
      clk = 0;
     # 17 reset = 1;
     # 11 reset = 0;
     # 29 reset = 1;
     # 11 reset = 0;
     # 300 $finish;
  end

  /* Make a regular pulsing clock. */
  always #5 clk = !clk;

  counter c1 (value, clk, reset);

endmodule // test

module counter(out, clk, reset);

  parameter WIDTH = 4;

  output [WIDTH-1 : 0] out;
  input 	       clk, reset;

  reg [WIDTH-1 : 0]   out;
  wire 	       clk, reset;

  always @(posedge clk)
    if (~reset)       
      out <= out + 1;

  always @(reset)     
    if (reset)        
      out <= 0;       


endmodule // counter